281 lines
25 KiB
Plaintext
281 lines
25 KiB
Plaintext
Analysis & Synthesis report for Chronometre
|
|
Wed Jan 24 17:21:59 2018
|
|
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
|
|
|
|
|
---------------------
|
|
; Table of Contents ;
|
|
---------------------
|
|
1. Legal Notice
|
|
2. Analysis & Synthesis Summary
|
|
3. Analysis & Synthesis Settings
|
|
4. Analysis & Synthesis Source Files Read
|
|
5. Analysis & Synthesis Resource Usage Summary
|
|
6. Analysis & Synthesis Resource Utilization by Entity
|
|
7. General Register Statistics
|
|
8. Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst4
|
|
9. Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst
|
|
10. Analysis & Synthesis Messages
|
|
|
|
|
|
|
|
----------------
|
|
; Legal Notice ;
|
|
----------------
|
|
Copyright (C) 1991-2009 Altera Corporation
|
|
Your use of Altera Corporation's design tools, logic functions
|
|
and other software and tools, and its AMPP partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Altera Program License
|
|
Subscription Agreement, Altera MegaCore Function License
|
|
Agreement, or other applicable license agreement, including,
|
|
without limitation, that your use is for the sole purpose of
|
|
programming logic devices manufactured by Altera and sold by
|
|
Altera or its authorized distributors. Please refer to the
|
|
applicable agreement for further details.
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Summary ;
|
|
+-----------------------------+----------------------------------------------+
|
|
; Analysis & Synthesis Status ; Successful - Wed Jan 24 17:21:59 2018 ;
|
|
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
|
|
; Revision Name ; Chronometre ;
|
|
; Top-level Entity Name ; CHRONO ;
|
|
; Family ; FLEX10K ;
|
|
; Total logic elements ; 69 ;
|
|
; Total pins ; 22 ;
|
|
; Total memory bits ; 0 ;
|
|
+-----------------------------+----------------------------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Settings ;
|
|
+--------------------------------------------------------------+-----------------+---------------+
|
|
; Option ; Setting ; Default Value ;
|
|
+--------------------------------------------------------------+-----------------+---------------+
|
|
; Device ; EPF10K70RC240-4 ; ;
|
|
; Top-level entity name ; CHRONO ; Chronometre ;
|
|
; Family name ; FLEX10K ; Stratix II ;
|
|
; Use smart compilation ; On ; Off ;
|
|
; Use Generated Physical Constraints File ; Off ; ;
|
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
|
; Preserve fewer node names ; On ; On ;
|
|
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
|
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
|
; VHDL Version ; VHDL93 ; VHDL93 ;
|
|
; State Machine Processing ; Auto ; Auto ;
|
|
; Safe State Machine ; Off ; Off ;
|
|
; Extract Verilog State Machines ; On ; On ;
|
|
; Extract VHDL State Machines ; On ; On ;
|
|
; Ignore Verilog initial constructs ; Off ; Off ;
|
|
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
|
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
|
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
|
; Parallel Synthesis ; Off ; Off ;
|
|
; NOT Gate Push-Back ; On ; On ;
|
|
; Power-Up Don't Care ; On ; On ;
|
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
|
; Remove Duplicate Registers ; On ; On ;
|
|
; Ignore CARRY Buffers ; Off ; Off ;
|
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore LCELL Buffers ; Off ; Off ;
|
|
; Ignore SOFT Buffers ; On ; On ;
|
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
|
; Auto Implement in ROM ; Off ; Off ;
|
|
; Optimization Technique ; Area ; Area ;
|
|
; Carry Chain Length ; 32 ; 32 ;
|
|
; Cascade Chain Length ; 2 ; 2 ;
|
|
; Auto Carry Chains ; On ; On ;
|
|
; Auto Open-Drain Pins ; On ; On ;
|
|
; Auto ROM Replacement ; On ; On ;
|
|
; Auto RAM Replacement ; On ; On ;
|
|
; Auto Clock Enable Replacement ; On ; On ;
|
|
; Strict RAM Replacement ; Off ; Off ;
|
|
; Auto Resource Sharing ; Off ; Off ;
|
|
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
|
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
|
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
|
|
; HDL message level ; Level2 ; Level2 ;
|
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
|
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
|
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
|
; Block Design Naming ; Auto ; Auto ;
|
|
; Synthesis Effort ; Auto ; Auto ;
|
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
|
+--------------------------------------------------------------+-----------------+---------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Source Files Read ;
|
|
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
|
|
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
|
|
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
|
|
; BoutonPoussoir2.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/BoutonPoussoir2.bdf ;
|
|
; DiviseurDeFrequence.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/DiviseurDeFrequence.bdf ;
|
|
; CheminDeDonnees.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/CheminDeDonnees.bdf ;
|
|
; CHRONO.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/CHRONO.bdf ;
|
|
; sequenceur2.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/sequenceur2.bdf ;
|
|
; 7446.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/7446.bdf ;
|
|
; 74168.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/74168.bdf ;
|
|
; 8count.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/8count.tdf ;
|
|
; aglobal.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/aglobal.inc ;
|
|
; f8count.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf ;
|
|
; 7456.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf ;
|
|
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
|
|
|
|
|
|
+----------------------------------------------------------------------+
|
|
; Analysis & Synthesis Resource Usage Summary ;
|
|
+-----------------------------------+----------------------------------+
|
|
; Resource ; Usage ;
|
|
+-----------------------------------+----------------------------------+
|
|
; Total logic elements ; 69 ;
|
|
; Total combinational functions ; 67 ;
|
|
; -- Total 4-input functions ; 32 ;
|
|
; -- Total 3-input functions ; 8 ;
|
|
; -- Total 2-input functions ; 6 ;
|
|
; -- Total 1-input functions ; 13 ;
|
|
; -- Total 0-input functions ; 8 ;
|
|
; Total registers ; 37 ;
|
|
; Total logic cells in carry chains ; 17 ;
|
|
; I/O pins ; 22 ;
|
|
; Maximum fan-out node ; DiviseurDeFrequence:inst1|inst10 ;
|
|
; Maximum fan-out ; 18 ;
|
|
; Total fan-out ; 257 ;
|
|
; Average fan-out ; 2.82 ;
|
|
+-----------------------------------+----------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
|
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
|
|
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
|
|
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
|
|
; |CHRONO ; 69 (0) ; 37 ; 0 ; 22 ; 32 (0) ; 2 (0) ; 35 (0) ; 17 (0) ; 0 (0) ; |CHRONO ; work ;
|
|
; |BoutonPoussoir2:inst15| ; 3 (3) ; 2 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|BoutonPoussoir2:inst15 ; work ;
|
|
; |BoutonPoussoir2:inst16| ; 2 (2) ; 2 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|BoutonPoussoir2:inst16 ; work ;
|
|
; |CheminDeDonnees:inst| ; 41 (0) ; 12 ; 0 ; 0 ; 29 (0) ; 0 (0) ; 12 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst ; work ;
|
|
; |74168:inst1| ; 10 (10) ; 4 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst1 ; work ;
|
|
; |74168:inst2| ; 8 (8) ; 4 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst2 ; work ;
|
|
; |74168:inst8| ; 9 (9) ; 4 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst8 ; work ;
|
|
; |7446:inst4| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|7446:inst4 ; work ;
|
|
; |7446:inst7| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|7446:inst7 ; work ;
|
|
; |DiviseurDeFrequence:inst1| ; 22 (1) ; 20 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 20 (1) ; 17 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1 ; work ;
|
|
; |7456:inst7| ; 3 (3) ; 3 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|7456:inst7 ; work ;
|
|
; |8count:inst4| ; 10 (0) ; 8 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 8 (0) ; 9 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst4 ; work ;
|
|
; |f8count:sub| ; 10 (10) ; 8 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 8 (8) ; 9 (9) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst4|f8count:sub ; work ;
|
|
; |8count:inst| ; 8 (0) ; 8 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; 8 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst ; work ;
|
|
; |f8count:sub| ; 8 (8) ; 8 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst|f8count:sub ; work ;
|
|
; |sequenceur2:inst17| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|sequenceur2:inst17 ; work ;
|
|
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
|
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
|
|
|
|
|
+------------------------------------------------------+
|
|
; General Register Statistics ;
|
|
+----------------------------------------------+-------+
|
|
; Statistic ; Value ;
|
|
+----------------------------------------------+-------+
|
|
; Total registers ; 37 ;
|
|
; Number of registers using Synchronous Clear ; 7 ;
|
|
; Number of registers using Synchronous Load ; 0 ;
|
|
; Number of registers using Asynchronous Clear ; 0 ;
|
|
; Number of registers using Asynchronous Load ; 0 ;
|
|
; Number of registers using Clock Enable ; 1 ;
|
|
; Number of registers using Preset ; 0 ;
|
|
+----------------------------------------------+-------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst4 ;
|
|
+------------------------+---------+--------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------+---------+--------------------------------------------------+
|
|
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
+------------------------+---------+--------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+------------------------------------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst ;
|
|
+------------------------+---------+-------------------------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------+---------+-------------------------------------------------+
|
|
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
+------------------------+---------+-------------------------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-------------------------------+
|
|
; Analysis & Synthesis Messages ;
|
|
+-------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus II Analysis & Synthesis
|
|
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
|
Info: Processing started: Wed Jan 24 17:21:56 2018
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre
|
|
Info: Found 1 design units, including 1 entities, in source file Decodeur.bdf
|
|
Info: Found entity 1: Decodeur
|
|
Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir.bdf
|
|
Info: Found entity 1: BoutonPoussoir
|
|
Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir2.bdf
|
|
Info: Found entity 1: BoutonPoussoir2
|
|
Info: Found 1 design units, including 1 entities, in source file DiviseurDeFrequence.bdf
|
|
Info: Found entity 1: DiviseurDeFrequence
|
|
Info: Found 1 design units, including 1 entities, in source file CheminDeDonnees.bdf
|
|
Info: Found entity 1: CheminDeDonnees
|
|
Warning: Can't analyze file -- file E:/SLEA/Sequenceur.bdf is missing
|
|
Info: Found 1 design units, including 1 entities, in source file CHRONO.bdf
|
|
Info: Found entity 1: CHRONO
|
|
Info: Found 1 design units, including 1 entities, in source file sequenceur2.bdf
|
|
Info: Found entity 1: sequenceur2
|
|
Info: Elaborating entity "CHRONO" for the top level hierarchy
|
|
Info: Elaborating entity "CheminDeDonnees" for hierarchy "CheminDeDonnees:inst"
|
|
Info: Elaborating entity "7446" for hierarchy "CheminDeDonnees:inst|7446:inst7"
|
|
Info: Elaborated megafunction instantiation "CheminDeDonnees:inst|7446:inst7"
|
|
Info: Elaborating entity "74168" for hierarchy "CheminDeDonnees:inst|74168:inst2"
|
|
Info: Elaborated megafunction instantiation "CheminDeDonnees:inst|74168:inst2"
|
|
Info: Elaborating entity "DiviseurDeFrequence" for hierarchy "DiviseurDeFrequence:inst1"
|
|
Info: Elaborating entity "8count" for hierarchy "DiviseurDeFrequence:inst1|8count:inst4"
|
|
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst4"
|
|
Info: Elaborating entity "f8count" for hierarchy "DiviseurDeFrequence:inst1|8count:inst4|f8count:sub"
|
|
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst4|f8count:sub", which is child of megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst4"
|
|
Info: Elaborating entity "8count" for hierarchy "DiviseurDeFrequence:inst1|8count:inst"
|
|
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst"
|
|
Info: Elaborating entity "7456" for hierarchy "DiviseurDeFrequence:inst1|7456:inst7"
|
|
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|7456:inst7"
|
|
Info: Elaborating entity "sequenceur2" for hierarchy "sequenceur2:inst17"
|
|
Info: Elaborating entity "BoutonPoussoir2" for hierarchy "BoutonPoussoir2:inst15"
|
|
Warning: Output pins are stuck at VCC or GND
|
|
Warning (13410): Pin "pointSeconde" is stuck at VCC
|
|
Warning (13410): Pin "pointDixieme" is stuck at GND
|
|
Info: Converted 2 single input CARRY primitives to CARRY_SUM primitives
|
|
Info: Implemented 91 device resources after synthesis - the final resource count might be different
|
|
Info: Implemented 3 input pins
|
|
Info: Implemented 19 output pins
|
|
Info: Implemented 69 logic cells
|
|
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
|
|
Info: Peak virtual memory: 199 megabytes
|
|
Info: Processing ended: Wed Jan 24 17:21:59 2018
|
|
Info: Elapsed time: 00:00:03
|
|
Info: Total CPU time (on all processors): 00:00:02
|
|
|
|
|