13 lines
60 KiB
Text
13 lines
60 KiB
Text
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 17:22:09 2018 " "Info: Processing started: Wed Jan 24 17:22:09 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
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{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "H " "Info: Assuming node \"H\" is an undefined clock" { } { { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "H" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "DiviseurDeFrequence:inst1\|7456:inst7\|5 " "Info: Detected ripple clock \"DiviseurDeFrequence:inst1\|7456:inst7\|5\" as buffer" { } { { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DiviseurDeFrequence:inst1\|7456:inst7\|5" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "DiviseurDeFrequence:inst1\|inst10 " "Info: Detected ripple clock \"DiviseurDeFrequence:inst1\|inst10\" as buffer" { } { { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 312 1216 1280 392 "inst10" "" } } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DiviseurDeFrequence:inst1\|inst10" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "H register DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8 register DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2 42.02 MHz 23.8 ns Internal " "Info: Clock \"H\" has Internal fmax of 42.02 MHz between source register \"DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8\" and destination register \"DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2\" (period= 23.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.700 ns + Longest register register " "Info: + Longest register to register delay is 19.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8 1 REG LC5_H27 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H27; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 448 1728 1792 528 "8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|245 2 COMB LC5_H27 2 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = LC5_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|245'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 608 1128 1176 640 "245" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 1.800 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|246 3 COMB LC6_H27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC6_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|246'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 920 1128 1176 952 "246" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 2.100 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|247 4 COMB LC7_H27 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 2.100 ns; Loc. = LC7_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|247'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 1232 1128 1176 1264 "247" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 2.400 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|248 5 COMB LC8_H27 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 2.400 ns; Loc. = LC8_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|248'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.
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{ "Info" "ITDB_TSU_RESULT" "BoutonPoussoir2:inst16\|inst BP2 H 0.100 ns register " "Info: tsu for register \"BoutonPoussoir2:inst16\|inst\" (data pin = \"BP2\", clock pin = \"H\") is 0.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.200 ns + Longest pin register " "Info: + Longest pin to register delay is 20.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns BP2 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'BP2'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BP2 } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 72 64 232 88 "BP2" "" } { 152 336 364 168 "BP2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(8.200 ns) + CELL(1.700 ns) 20.200 ns BoutonPoussoir2:inst16\|inst 2 REG LC1_H32 2 " "Info: 2: + IC(8.200 ns) + CELL(1.700 ns) = 20.200 ns; Loc. = LC1_H32; Fanout = 2; REG Node = 'BoutonPoussoir2:inst16\|inst'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.900 ns" { BP2 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns ( 59.41 % ) " "Info: Total cell delay = 12.000 ns ( 59.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns ( 40.59 % ) " "Info: Total interconnect delay = 8.200 ns ( 40.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "20.200 ns" { BP2 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "20.200 ns" { BP2 {} BP2~out {} BoutonPoussoir2:inst16|inst {} } { 0.000ns 0.000ns 8.200ns } { 0.000ns 10.300ns 1.700ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.600 ns + " "Info: + Micro setup delay of destination is 2.600 ns" { } { { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H destination 22.700 ns - Shortest register " "Info: - Shortest clock path from clock \"H\" to destination register is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!;
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{ "Info" "ITDB_FULL_TCO_RESULT" "H b1 CheminDeDonnees:inst\|74168:inst1\|49 40.800 ns register " "Info: tco from clock \"H\" to destination pin \"b1\" through register \"CheminDeDonnees:inst\|74168:inst1\|49\" is 40.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H source 22.700 ns + Longest register " "Info: + Longest clock path from clock \"H\" to source register is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.400 ns) 13.300 ns DiviseurDeFrequence:inst1\|inst10 3 REG LC1_H27 18 " "Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|inst10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 } "NODE_NAME" } } { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 312 1216 1280 392 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(9.400 ns) + CELL(0.000 ns) 22.700 ns CheminDeDonnees:inst\|74168:inst1\|49 4 REG LC1_H33 11 " "Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H33; Fanout = 11; REG Node = 'CheminDeDonnees:inst\|74168:inst1\|49'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.400 ns" { DiviseurDeFrequence:inst1|inst10 CheminDeDonnees:inst|74168:inst1|49 } "NODE_NAME" } } { "74168.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/74168.bdf" { { 680 1264 1328 760 "49" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 25.11 % ) " "Info: Total cell delay = 5.700 ns ( 25.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "17.000 ns ( 74.89 % ) " "Info: Total interconnect delay = 17.000 ns ( 74.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 CheminDeDonnees:inst|74168:inst1|49 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} CheminDeDonnees:inst|74168:inst1|49 {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } } 0 0 "%
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{ "Info" "ITDB_TH_RESULT" "BoutonPoussoir2:inst15\|inst BP1 H 5.700 ns register " "Info: th for register \"BoutonPoussoir2:inst15\|inst\" (data pin = \"BP1\", clock pin = \"H\") is 5.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H destination 22.700 ns + Longest register " "Info: + Longest clock path from clock \"H\" to destination register is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.400 ns) 13.300 ns DiviseurDeFrequence:inst1\|inst10 3 REG LC1_H27 18 " "Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|inst10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 } "NODE_NAME" } } { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 312 1216 1280 392 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(9.400 ns) + CELL(0.000 ns) 22.700 ns BoutonPoussoir2:inst15\|inst 4 REG LC1_H39 9 " "Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H39; Fanout = 9; REG Node = 'BoutonPoussoir2:inst15\|inst'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.400 ns" { DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 25.11 % ) " "Info: Total cell delay = 5.700 ns ( 25.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "17.000 ns ( 74.89 % ) " "Info: Total interconnect delay = 17.000 ns ( 74.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} BoutonPoussoir2:inst15|inst {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info"
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{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Peak virtual memory: 156 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 17:22:10 2018 " "Info: Processing ended: Wed Jan 24 17:22:10 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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