library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY Sequenceur_vhdl is 

port(
		H, BP1, BP2: in std_logic;
		Count, Reset: out std_logic
);
END;

ARCHITECTURE Sequenceur_vhdl of Sequenceur_vhdl is
	
BEGIN
	
	PROCESS(H)
	
		
	
		